In relation to a system including a plurality of arithmetic processing devices, such as central processing units (CPUs), there is proposed a method of detecting a failure of any of the arithmetic processing devices and replacing the failed arithmetic processing device with another arithmetic processing device (see, for example, Japanese Laid-open Patent Publication No. 2004-318885).
When the failed arithmetic processing device is replaced with another arithmetic processing device, physical connections of those arithmetic processing devices are changed. Accordingly, the system changes information, such as numbers, specifically assigned to the relevant arithmetic processing devices, and makes each arithmetic processing device recognize the changed information, thus enabling communication to be performed between the arithmetic processing devices after the replacement of the failed arithmetic processing device. In other words, when the failed arithmetic processing device is replaced with another one, information set in each of the arithmetic processing devices within the system is updated.